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    1 {-# LANGUAGE AllowAmbiguousTypes #-}
    2 {-# LANGUAGE OverloadedStrings #-}
    3 {-# LANGUAGE QuasiQuotes #-}
    4 
    5 {- |
    6 Module      : NITTA.Project.VerilogSnippets
    7 Description : Snippets for Verilog code-generation
    8 Copyright   : (c) Aleksandr Penskoi, 2019
    9 License     : BSD3
   10 Maintainer  : aleksandr.penskoi@gmail.com
   11 Stability   : experimental
   12 -}
   13 module NITTA.Project.VerilogSnippets (
   14     snippetClkGen,
   15     snippetDumpFile,
   16 ) where
   17 
   18 import Data.String.Interpolate
   19 import Data.Text qualified as T
   20 
   21 snippetClkGen :: T.Text
   22 snippetClkGen =
   23     [__i|
   24         initial begin
   25             clk = 1'b0;
   26             rst = 1'b1;
   27             repeat(4) \#1 clk = ~clk;
   28             rst = 1'b0;
   29             forever \#1 clk = ~clk;
   30         end
   31     |]
   32 
   33 snippetDumpFile :: T.Text -> T.Text
   34 snippetDumpFile mn =
   35     [__i|
   36         initial begin
   37             $dumpfile("#{ mn }_tb.vcd");
   38             $dumpvars(0, #{ mn }_tb);
   39         end
   40     |]